`timescale 1ns/1ns
//behavioral case to assert z1 in state y1y2y3 = 110
module a_gt_eq_6_case (rst_n, clk, y, x1, z1);
input rst_n, clk, x1; //define inputs and output
output [2:0] y;
output z1;
reg [2:0] y, next_state;
wire z1;

//assign state codes
parameter state_a = 3'b000,
          state_b = 3'b001,
          state_c = 3'b011,
          state_d = 3'b010,
          state_e = 3'b110;
assign z1 = (y == state_e) ? 1'b1 : 1'b0; //define output z1

always @ (posedge clk) begin //set next state 
    if(rst_n == 0) 
        y <= state_a;
    else 
        y <= next_state;
end

always @ (*) begin //determine next state 
    case (y)
    state_a:
        next_state = (x1) ? state_c : state_b;
    state_b:
        next_state = state_d;
    state_c: 
        next_state = (x1) ? state_e : state_d;
    state_d, state_e: 
        next_state = state_a;
    default:
        next_state = state_a;
    endcase
end

endmodule

//test bench to assert z1 in state y1y2y3 = 110
module a_gt_eq_6_case_tb;
reg rst_n, clk, x1; //inputs are reg for test bench
wire [2:0] y; //outputs are wire for test bench
wire z1;

initial //display variables
    $monitor ("x1 = %b, state = %b, z1 = %b", x1, y, z1);

initial begin //define clock
    clk = 1'b0;
    forever #10 clk = ~clk;
end

//define input sequence
initial begin
    #0 rst_n = 1'b0;
    x1 = 1'b0;
    #10 rst_n = 1'b1;
    x1 = 1'b0;
    @ (posedge clk)
    x1 = 1'b1;
    @ (posedge clk)
    x1 = 1'b0;
    @ (posedge clk)
    x1 = 1'b1;
    @ (posedge clk)
    x1 = 1'b0;
    @ (posedge clk)
    x1 = 1'b1;
    @ (posedge clk)
    x1 = 1'b1;
    @ (posedge clk)
    x1 = 1'b1;
    @ (posedge clk)
    x1 = 1'b1;
    @ (posedge clk)
    x1 = 1'b0;
    @ (posedge clk)
    #10 $finish;
end

//instantiate the module into the test bench
a_gt_eq_6_case inst1 (rst_n, clk, y, x1, z1);

initial begin
    $dumpfile("a_gt_eq_6_case_tb.vcd"); //生成的 vcd 文件名称
    $dumpvars(0, a_gt_eq_6_case_tb); //测试模块名称
end

endmodule